Bipolar transistor manufacturing

ABSTRACT

A method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming, by epitaxy, the transistor base in the form of a single-crystal semiconductor multilayer including at least a lower layer, a heavily-doped median layer of the second conductivity type, and an upper layer that contacts a heavily-doped emitter of the first conductivity type.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to the manufacturing of junction components intended to be very fast and thus especially requiring a very thin base. The junction can be a homo-junction or a hetero-junction, that is, a junction between regions formed of a same semiconductor or of distinct semiconductors. More specifically, the present invention relates to the manufacturing of bipolar transistors with a silicon emitter and collector and a base formed by a silicon epitaxy (homo-epitaxy) or a silicon-germanium epitaxy (hetero-epitaxy).

[0003] 2. Discussion of the Related Art

[0004] Upon formation of such a bipolar transistor, a P-type doped base is formed by epitaxy, on a single-crystal silicon semiconductor substrate of a first conductivity type, for example, N. In subsequent anneals, the P-type doping atoms, generally boron, tend to diffuse from the base layer, on the one hand, towards the underlying substrate (collector) and, on the other hand, towards the superposed emitter. It is thus difficult to obtain a base which is thin and heavily doped.

[0005] To enable reduction of the base thickness and, more specifically, to avoid the boron atoms placed in the base at the time of its formation diffuse into the underlying collector, it has been provided in unpublished French patent application No. 9,912,115 filed on Sep. 29, 1999 by France Télécom and the Commissariat à l'Energie Atomique, to implant carbon atoms into a silicon-germanium base.

[0006] It is indeed known that carbon atoms substitute to interstitial silicon atoms more easily than dopant atoms such as boron and limit the diffusion of boron.

[0007] However, the carbon must be implanted into the silicon-germanium base. Its implantation is thus performed at relatively high doses and powers (for example, 1015 atoms/cm² under 35 keV). Such an implantation creates many defects in the crystal lattice structure of the base. To enable reorganization of the lattice and totally “repair” such defects, the structure would have to be submitted to a relatively long anneal at a high temperature, which is impossible if the diffusion of boron is desired to be limited. The base thus inevitably has many crystal defects, which adversely affects the transistor performance. Such defects also appear in the case of a homo-junction transistor having a silicon base.

SUMMARY OF THE INVENTION

[0008] The present invention thus aims at providing a novel bipolar transistor manufacturing method which enables obtaining a thin and heavily-doped base.

[0009] The present invention also aims at such a method which enables obtaining a relatively homogeneous base with no defects.

[0010] To achieve these and other objects, the present invention provides a method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming by epitaxy the transistor base in the form of a single-crystal semiconductor multilayer including at least a lower layer, a heavily-doped median layer of the second conductivity type, and an upper layer that contacts a heavily-doped emitter of the first conductivity type.

[0011] According to an embodiment of the present invention, the step of carbon implantation at the substrate surface includes implanting a dose of from 2 to 8.10¹⁴ atoms/cm² at a power lower than 20 keV, preferably ranging between 2 and 10 keV.

[0012] According to an embodiment of the present invention, the method further includes the steps of:

[0013] defining an emitter window;

[0014] depositing a conductive material to fill up the window, etching it and forming spacers at the periphery of the conductive material;

[0015] forming in the substrate, on either side of the window, an extrinsic base area; and

[0016] annealing.

[0017] According to an embodiment of the present invention, the step of defining the emitter window includes the steps of:

[0018] depositing a first insulating layer;

[0019] depositing a second insulating layer selectively etchable with respect to the first layer; and

[0020] etching the first and second insulating layers to partially expose a selected region of the upper layer.

[0021] According to an embodiment of the present invention, the first insulating layer is silicon oxide and the second insulating layer is silicon nitride.

[0022] According to an embodiment of the present invention, the multilayer is made of silicon.

[0023] According to an embodiment of the present invention, the multilayer includes germanium.

[0024] According to an embodiment of the present invention, the lower layer is a silicon-germanium layer of a thickness on the order of 20 nm; the median layer is a silicon-germanium layer of a thickness on the order of 10 nm; and the upper layer is a silicon or silicon-germanium layer of a thickness on the order of 15 nm.

[0025] The present invention also provides a bipolar hetero-junction transistor, including a collector buried in a silicon substrate, a silicon base multilayer formed by epitaxy on the substrate and underlying a silicon emitter, the substrate surface further including an area in which carbon atoms are present.

[0026] According to an embodiment of the present invention, the multilayer includes germanium.

[0027] The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments, in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028]FIGS. 1A to 1D illustrate, in a partial simplified cross-section view, a bipolar transistor at different steps of its manufacturing according to the present invention.

DETAILED DESCRIPTION

[0029] As usual in the representation of integrated circuit, the drawings are not to scale. Further, the same references designate the same elements.

[0030] As illustrated in FIG. 1A, an active region is first defined in a silicon substrate 1. The active region is delimited, for example, by silicon oxide (SiO₂) field insulation areas 2. Substrate 1 is lightly doped and of a first conductivity type, for example N. The substrate is intended for forming the collector of the final bipolar transistor. According to the present invention, carbon is implanted into substrate 1. This implantation is performed at small dose and low power in a surface area 3 of small thickness. Area 3 is, for example, formed by implanting from 1 to 10.10¹⁴ atoms/cm², preferably from 2 to 8.1014 at./cm², of carbon at a power under 20 keV, preferably between 2 and 10 keV.

[0031] An anneal for “repairing” the surface defects of substrate 1 caused by the carbon implantation is then performed. Such an anneal is performed in temperature conditions adapted to enable homogeneous recrystallization of the substrate while avoiding formation therein of silicon carbide (SiC) precipitates. This anneal can be performed with no specific constraints since, at this manufacturing stage, the structure includes no junction. Further, the carbon implantation being performed at low power and low dose, the proportion of defects is relatively small. An anneal at a temperature on the order of 900° C. for approximately 30 s may for example be performed.

[0032] At the next steps, illustrated in FIG. 1B, a single-crystal semiconductor base multilayer T is formed by successive epitaxial depositions. Multilayer T includes at least, from bottom to top, a lower layer 4 in contact with substrate 1, that is, with surface layer 3 including the carbon atoms, a median layer 5 and an upper layer 6. Lower layer 4 is undoped or slightly doped. Median layer 5 is very heavily doped and of the conductivity type opposite to that of underlying substrate 1. For example, layer 5 is P-type doped (P+), for example with boron. Upper layer 6 may be P-type doped.

[0033] At the next steps illustrated in FIG. 1C, a layer 7 of a first insulating material, followed by a layer 8 of a second insulating material, are successively deposited. The first and second materials are selectively etchable with respect to each other. Layer 7 is selectively etchable with respect to upper layer 6 of underlying multilayer T. The insulating materials of layers 7 and 8 are also selectively etchable with respect to a subsequently-deposited material.

[0034] Layer 7 and 8 are etched to define an emitter window. N-type dopants are then implanted at high dose and high energy to form, in substrate 1, under the emitter window, a buried collector area (not shown).

[0035] A silicon layer 9 is then deposited to form an emitter. Layer 9 is then etched to extend beyond either side of the emitter window (FIG. 1C shows the structure after this etching). The emitter region 9 thus formed has, above base-emitter junction 6-9, a single-crystal structure area 91 and, on insulating layer 8, a multiple-crystal or amorphous structure area 92. Emitter region 9 is heavily doped of type N, for example, with arsenic.

[0036] At the next steps, illustrated in FIG. 1D, a spacer 10 is formed around emitter region 9. Spacer 10 is, for example, of same nature as underlying insulating layer 8. Said layer is then simultaneously removed everywhere, except around emitter 9, under spacer 10, as well as the underlying portions of layer 7.

[0037] Boron is then implanted at high dose on either side of emitter region 9 and of underlying collector-base junction 1-4. A heavily-doped extrinsic base region 11 of the transistor is thus formed.

[0038] This implantation forming extrinsic base 11 must be followed by an activation anneal. During this anneal, doping boron atoms tend to diffuse and thus to widen the heavily-doped base region 5 by having boron atoms dope the portion of N layer 4 and of substrate 1 under region 5 in the area located under the emitter window. This diffusion would result from a double phenomenon: direct vertical diffusion of the boron atoms and lateral diffusion of interstitial silicon atoms from the disturbed region where the extrinsic base implantation has been performed, these interstitial atoms then favoring the diffusion of boron from layer 5 to layer 4 and substrate 1.

[0039] The carbon atoms located in region 3 appear to enable thwarting the two above-mentioned effects. Thus, carbon atoms, by their reaction with the interstitial silicon atoms, enable blocking the diffusion of these interstitial atoms, but probably also have an effect upon the direct diffusion of boron.

[0040] Thus, the present invention enables submitting the structure to an anneal of a duration and temperature appropriate to an adequate activation of the arsenic in emitter 9 and of the boron in extrinsic base 11 without causing any undesirable extension of the intrinsic base. In the case of a BICMOS technology, this anneal can also be adapted to the activation of boron and of arsenic in MOS transistors. All other things being equal, the carbon of surface area 3 of substrate 1 (collector) thus enables reducing the thickness of the base with respect to a transistor obtained with conventional methods. Due to the carbon of area 3, it is also advantageously possible to increase the doping median layer 5 without causing any widening of the base with respect to a transistor obtained with conventional methods. The performances of the resulting transistors are improved.

[0041] As an non-limiting example, base multilayer T may include a lower silicon-germanium layer 4 having a thickness on the order of 20 nm, a silicon-germanium intrinsic base median layer 5 having a thickness on the order of 10 nm, and an upper silicon or silicon-germanium layer 6 with a thickness on the order of 15 nm. Layer 7 is a silicon oxide layer. Layer 8 is a silicon nitride layer (Si₃N₄). Spacer 10 is made of silicon nitride and enables spacing extrinsic base 11 apart from collector-base junction 1-4 by approximately 0.2 μm.

[0042] Of course, the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. In particular, the foregoing description relates to a specific case of formation of a bipolar transistor with a silicon/silicon-germanium hetero-junction as a non-limiting example only. Those skilled in the art should understand that the specific described method can be adapted according to the considered technological process. For example, the base multilayer may include an additional undoped silicon layer interposed between the substrate (collector) and lower undoped or slightly doped silicon germanium layer 4.

[0043] Further, those skilled in the art should understand that the present invention relates to the forming of any junction by epitaxy of a single-crystal layer on a single-crystal substrate. Thus, as also indicated previously, the present invention not only applies to hetero-junction components, but also to homo-junction components. For example, the base multilayer may be formed by epitaxy of various silicon layers, each of these layers being doped differently.

[0044] In other words, and more generally, the base multilayer is formed of various regions of a first single-crystal semiconductor (silicon in the considered case) in which profiles of dopants (boron) and of at least one second single-crystal semiconductor (germanium) distinct from the first one may be adapted in any appropriate manner according to the technological line and to the desired performances. The germanium and boron profiles may be complex and include areas with a gradual composition.

[0045] Further, before any implantation operation, a specific step of formation of a thin sacrificial protection and surface reconcentration insulator may be provided. For example, before forming surface area 3 including carbon, a silicon oxide will be grown by fast thermal processing. This sacrificial oxide will be subsequently removed before the base forming epitaxy.

[0046] Moreover, the forming of the buried collector may be carried out in two implantations, a first implantation being performed before formation of area 3, and followed by the implantation through the window such as previously described.

[0047] Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto. 

What is claimed is:
 1. A method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming, by epitaxy, a transistor base in the form of a semiconductor multilayer including at least a lower layer, a heavily-doped median layer of the second conductivity type, and an upper layer that contacts a heavily-doped emitter of the first conductivity type.
 2. The method of claim 1, wherein the step of carbon implantation at the substrate surface includes implanting a dose of from 2 to 8.1014 atoms/cm² at a power lower than 20 keV, preferably ranging between 2 and 10 keV.
 3. The method of claim 1, further including the steps of: defining an emitter window; depositing a conductive material to fill up the window, etching it and forming spacers at the periphery of the conductive material; forming in the substrate, on either side of the window, an extrinsic base area; and annealing.
 4. The method of claim 3, wherein the step of defining of the emitter window includes the steps of: depositing a first insulating layer; depositing a second insulating layer selectively etchable with respect to the first layer; and etching the first and second insulating layers to partially expose a selected region of the upper layer.
 5. The method of claim 4, wherein the first insulating layer is silicon oxide and the second insulating layer is silicon nitride.
 6. The method of claim 1, wherein the multilayer is made of silicon.
 7. The method of claim 1, wherein the multilayer includes germanium.
 8. The method of claim 1, wherein the lower layer is a silicon-germanium layer of a thickness on the order of 20 nm; wherein the median layer is a silicon-germanium layer of a thickness on the order of 10 nm; and wherein the upper layer is a silicon or silicon-germanium layer of a thickness on the order of 15 nm.
 9. A bipolar hetero-junction transistor, including a collector buried in a silicon substrate, a silicon base multilayer formed by epitaxy on the substrate and underlying a silicon emitter, the substrate surface further including an area in which carbon atoms are present.
 10. The transistor of claim 9, wherein the multilayer includes germanium. 